The ADSP-21991 integrates the fixed point ADSP-219x family base architecture with a serial port, an SPI compatible port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, onchip program and data memory spaces, and a complete set of embedded control peripherals that permits fast motor control and signal processing in a highly integrated environment.
The ADSP-21991 architecture is code compatible with previous ADSP-217x based ADMCxxx products. Although the architectures are compatible, the ADSP-21991, with ADSP-219x architecture, has a number of enhancements over earlier architectures. The enhancements to computational units, data address generators, and program sequencer make the ADSP-21991 more flexible and easier to program than the previous ADSP-21xx embedded DSPs.
Indirect addressing options provide addressing flexibility premodify with no update, pre- and post-modify by an immediate 8-bit, twos complement value and base address registers for easier implementation of circular buffering.
The ADSP-21991 integrates 40K words of on-chip memory configured as 32K words (24-bit) of program RAM, and 8K words (16-bit) of data RAM.
Fabricated in a high speed, low power, CMOS process, the ADSP-21991 operates with a 6.25ns instruction cycle time for a 160MHz CCLK and with a 6.67ns instruction cycle time for a 150MHz CCLK. All instructions, except two multiword instructions, execute in a single DSP cycle.
